Addition/Subtraction of Logarithmic Number System
نویسندگان
چکیده
This paper tells the technique for low power addition/subtraction of Logarithmic number system (LNS). Firstly, the impact of partitioning the look up tables (LUT) required for addition/subtraction on complexity, performance is studied. Two design parameters namely organisation of word and base are also taken into consideration. For addition and subtraction of LNS, MATLAB is also used to calculate the output which is further stored in partitioned LUTs. The results are obtained through Verilog code written in Xilinx (version-ISE-13.2) and implemented in FPGA. Index: FPGA, LUT, LNS
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